The paper discusses various clock tree synthesis problems related to the robustness in sub-micron design nodes. The topic discussed include the clock polarity assignment problem for addressing the noise in power/ground, clock mesh design and synthesis problem for addressing the variation in clock delays and adjustable buffer delay assignment in order to support multi-voltage mode designs and parameters. The paper talks about the clock tree synthesis and the issues and difficulties faced because of the requirement of clock balancing. There are various parameters to improve the quality of the clock tree. It is important to have a reduced pessimism in the work optimization problems and the proposed techniques with regard to the circuit reliability in deep submicron design technology. The following subsections cover 1) the clock polarity assignment problem for reducing peak current noise on the clock tree. 2) the adjustable delay buffer (ADB) allocation and assignment problem that is useful in the multiple voltage modes design environment.