High-Speed and Low-power are the major challenges for today’s electronics industries. Power dissipation is an important consideration in terms of Speed/Performance and space for VLSI Chip design. Power management techniques are generally used to designing low power circuits and systems. This thesis presents the various VLSI Design Methodologies for high Speed and Low power management techniques that can meet future challenges to designs low power high speed/performance circuits, algorithm level design. It also describes the many issues regarding circuits design at architectural, logic and device levels and presents various techniques to overcome difficulties.